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SPIの前は何が使われていた? 調査メモ  

最終更新日: 2018/04/14 10:35

Sorry. This article is now writing!
SPIの前は何が使われていた?



■Firmware Hub(FWH)
 FWHはBIOSやPOSTなどのプログラムを格納するフラッシュメモリとしての役割を持っている。こうしたフラッシュメモリはこれまではISAバス(Xバス)経由で接続されることが多かったが、FWHはICHに直結されており、ISAバスを必要としない。2種類あるFWH(82802ABと82802AC)の違いは、このフラッシュメモリの容量であり、82802ABが512Mbytes、82802ACが1Mbytesである。  FWHはフラッシュメモリ以外にRandom Number Generator(RNG)というハードウェアによる乱数発生回路を内蔵しており、暗号化などセキュリティの強化に利用できる。

@IT > @IT総合検索 > Insider's Computer Dictionary > [Intel 810] 最終更新日: 2002/05/29
http://www.atmarkit.co.jp/icd/root/17/7885617.html









【CeBIT 2004】Intelが次世代チップセットIntel 925X/915シリーズを公開

Intel® 5 Series Chipset and
Intel® 3400 Series Chipset
Datasheet
January 2012


5.24 Serial Peripheral Interface (SPI)

5.24.1.2 Descriptor Mode
Descriptor Mode is required for all SKUs of the PCH. It enables many new features of
the chipset:
• Integrated Gigabit Ethernet and Host processor for Gigabit Ethernet Software
• Intel® Active Management Technology
• Intel® Quiet System Technology
• Intel® Management Engine Firmware
• PCI Express* root port configuration
• Supports up to two SPI components using two separate chip select pins
• Hardware enforced security restricting master accesses to different regions
• Chipset Soft Strap regions provides the ability to use Flash NVM as an alternative to
hardware pull-up/pull-down resistors for the PCH and Processor
• Supports the SPI Fast Read instruction and frequencies of up to 33 MHz
Uses standardized Flash Instruction Set



5.24.1.2.1 SPI Flash Regions
In Descriptor Mode the Flash is divided into five separate regions:

Region Content
0 Flash Descriptor
1 BIOS
2 Management Engine
3 Gigabit Ethernet
4 Platform Data

Only three masters can access the four regions: Host processor running BIOS code,
Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and
Management Engine. The only required region is Region 0, the Flash Descriptor. Region
0 must be located in the first sector of device 0 (offset 0). 


Flash Region Sizes
SPI flash space requirements differ by platform and configuration. The Flash Descriptor
requires one 4 KB or larger block.

5.24.2 Flash Descriptor
The maximum size of the Flash Descriptor is 4 KB. If the block/sector size of the SPI
flash device is greater than 4 KB, the flash descriptor will only use the first 4 KB of the
first block. The flash descriptor requires its own block at the bottom of memory (00h).
The information stored in the Flash Descriptor can only be written during the
manufacturing process as its read/write permissions must be set to Read only when the
computer leaves the manufacturing floor.

The Flash Descriptor is made up of eleven sections (see Figure 5-13). 

1. The Flash signature selects Descriptor Mode as well as verifies if the flash is
programmed and functioning. The data at the bottom of the flash (offset 0) must be
0FF0A55Ah to be in Descriptor mode. 

2. The Descriptor map has pointers to the other five descriptor sections as well as the
size of each.


4. The Region section points to the three other regions as well as the size of each
region. 

5. The master region contains the security settings for the flash, granting read/write
permissions for each region and identifying each master by a requestor ID. See
Section 5.24.2.1 for more information.

6 & 7. The Processor and PCH chipset soft strap sections contain Processor and PCH
configurable parameters. 








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